1. Field of the Invention
This invention relates to integrated circuit memory devices and to corresponding systems and methods of operating.
2. Discussion of the Related Art
Communication systems that have to process data streams require memories to hold incoming and outgoing data. Due to the irregular flow of data streams, e.g. packets of data arriving at irregular time intervals, this data is held often in temporary storage until the main processor is ready to retrieve it and process it. Known memory types include the following:
FIFO: (First in First out) Allows storing incoming data until needed, or ready to process. Its main drawback is that when the data is needed it still needs to be retrieved and stored in a second memory. Thus more memory is used then actually needed. Add to that the fact that copying data takes time as well
DMA: (Direct Memory Access) here no temporary buffer is used but data is directly written into the processor's main memory. The main drawback is that during this operation the processor is idle. It cannot access its memory. Furthermore the DMA access is ‘dangerous’, If not closely controlled by software the risk exists that data is overwritten. Software also requires execution which takes time.
Dual Port Ram (DPR): This has no sequential input. This can be solved using additional logic but it requires components. Also the DPR is not fully used. Since both sides are read/write and only one side is used in READ mode and the other in WRITE mode half of its capability is not used. Furthermore there is no mechanism to hold off incoming data when the memory is full, Software will be required to handshake, which will again take execution time.
U.S. Pat. No. 4,827,473 shows a packet switching system having a receive packet storing circuit provided with a receive packet buffer of a first-in random out (FIRO) memory, and a transmit packet storing circuit provided with a transmit packet buffer of the FIRO memory. The FIRO memory has discrete components making up a FIRO controller (FIROC) and a conventional single port RAM. The FIROC has counters for generating write addresses for the RAM, and other RAM control signals, and interfaces to receive random read addresses from other devices, to read out packets stored in the RAM. The address space of the RAM, consists of 256 blocks of 4,096 bytes each. The FIROC is provided with a level 2 interface (L2INF), a microprocessor interface (μPINF), a bus interface (BINF), a data selector (DSEL) for the RAM, and an address selector (ASEL) for the RAM, an arbiter circuit (ARB) for contention among read out or write in signals from the L2INF, μPINF and BINF to the RAM.
There remains a need for improved devices.